1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor memory device and a method for operating the same.
2. Description of the Related Art
A semiconductor memory device, including a dynamic random access memory (DRAM), receives write data from a chipset (a memory controller) and transfers read data to the chipset. Here, the semiconductor memory device and the chipset may operate in synchronization with a system clock. However, when data is transferred from the chipset to the semiconductor memory device, data and a system clock may have different loads and signal traces. In addition, due to positional differences in transferring a system clock to a plurality of memories, a skew occurs between the data and the system clock.
In order to reduce the skew between the data and the system clock, a data strobe signal (DQS) is transferred together with the data when the data is transferred from the chipset to the semiconductor memory device. The data strobe signal (DQS) is also called an “echo clock”. Since the data strobe signal (DQS) has the same load and signal trace as the data, the skew between the system clock and the data can be minimized by strobing data using the data strobe signal (DQS) in the semiconductor memory device.
Meanwhile, according to an example, the data strobe signal (DQS) toggles, for example, only in a set period. At this time, in toggling data strobe signal (DQS), when a high impedance (Hi-Z) state is to be entered after the last clock edge, a ringing often occurs. This phenomenon is called a write postamble ringing. More specifically, the data strobe signal (DQS) may not return to the high impedance (Hi-Z) state after the completion of the toggling when glitch occurs in the data strobe signal (DQS) due to noise. When the data strobe signal (DQS) is transferred, such a ringing may be generated due to characteristics of a transmission line or characteristics of a buffer for interfacing the data strobe signal (DQS).
Therefore, techniques for preventing the write postamble ringing have been developed. As an example of such a technique, a method of filtering a data strobe signal (DQS) may be used. Here, a filtering signal corresponding to a burst length is generated, and a data strobe signal (DQS) output period is limited according to the filtering signal. Therefore, even though glitch occurs in the postamble period of the data strobe signal (DQS), the write postamble ringing phenomenon can be prevented using the above-described filtering method.
However, the conventional filtering method also has the following features.
The filtering signal for filtering the data strobe signal (DQS) is generated in a clock domain because the data strobe signal (DQS) toggles during an appropriate period corresponding to the burst length and has a high impedance (Hi-Z) state in the remaining period. Here, the completion point of time for the write operation may not be accurately determined by using the data strobe signal (DQS). Accordingly, since a write command is applied in synchronization with a clock, the filtering signal is generated by calculating the completion point of time for the write operation by using the clock. However, since the domains of the clock and the data strobe signal (DQS) are different, a skew may occur between the data strobe signal (DQS) and the filtering signal generated in the clock domain. Accordingly, the data strobe signal (DQS) is not appropriately filtered, and the postamble ringing phenomenon may not be prevented.
Meanwhile, in order to address the above-described features, different domain signals are synchronized. However, since a signal delay and a probability for malfunctions increase due to such synchronizing operations, a high speed operation of a semiconductor device may not be achieved and current consumption may increase.